The UP Electrical and Electronics Engineering Institute (UP EEEI), through the Philippine Institute for Integrated Circuits (PIIC), in partnership with the Advanced Science and Technology Institute of the Department of Science and Technology (DOST-ASTI), trained 26 representatives from ASEAN member states on Modern Very Large-Scale Integration (VLSI) Design. The training, which ran from 25 to 29 September 2017, was held in the National Engineering Center, University of the Philippines Diliman.
Faculty with specialization on integrated circuit (IC) design facilitated the workshop of eight delegates from Laos (National University of Lao and Ministry of Science and Technology), seven from Myanmar (University of Computer Studies, Computer University in Myitkyina, and Technological University in Meiktila and Hmawbi), seven from Cambodia (University of Technology of Cambodia), and four Filipinos from DOST-ASTI.
VLSI is the process of creating an IC by combining many transistors into a single chip. With the increasing complexity of digital systems, the participants were trained on computer-aided design tools to minimize time and cost of design entry, verification, and automation of hardware generation.
The training focused on the use of Verilog Hardware Design Language (HDL) to describe and to write complex digital circuits. Specifically, the participants were trained on the following topics: Hardware Description Languages; Transistor and Transistor Parasitics; Logic Functions, Layout Stick Diagrams, Wires, Vias, and Standard Cells; Combinational Logic Networks and Power Optimization; Programmable Devices; Combinational Testing and Datapath Design; Combinational Circuits; Sequential Circuits; Finite State Machines, and Subsystem Design, Floorplanning, and CAD Systems.
The participants shared that they consider the training challenging. Despite that, they noted that the knowledge gained would improve the curricula and the IC design practice in their respective universities.
The organizers welcomed the participants through a Cultural Night on the second day, which featured the performances of the UP Staff Chorale and the UP Filipiniana Dance Group. The event was also graced by the presence of Dr. Leah Buendia (DOST Assistant Secretary for International Cooperation), Engr. Peter Antonio Banzon (DOST-ASTI RDD Chief Science Research Specialist), Dr. Evangeline Amor (UPD Vice Chancellor for Academic Affairs), and Dr. Rhandley Cajote (UP College of Engineering Associate Dean for Student Affairs), who also gave their respective messages for the participants.
The participants also had a chance to tour UP Diliman and the UP-Analog Devices Microelectronics Laboratory in UP EEEI on the fourth day of the workshop.
The DOST through DOST-ASTI funded the training, with the Tourism Promotions Board Philippines (TPB) providing the tokens for the participants.